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ArctIC
is a static rule checker that can be used to check SOC designs
against electrical rules. The rules include both built-in checks
and user written rules. The built-in checks include checks for
issues related to circuit topology (e.g. incorrect transistor
sizing), timing (e.g. latch writability) and noise immunity (e.g.
charge sharing). User written rules can include design methodology
checks plus additional electrical checks that are pertinent to the
circuit design style being used.
For
more information on ArctIC please
contact CadMOS Design Technology Inc. phone: +1-408-795-1212 or
email: info@cadmos.com
Send
Mail to webmaster@cadmos.com
with questions or comments about this web site.
Copyright
(c) 2000, CadMOS Design Technology Inc. Last modified May 22,
2000 |
