Monday, Jun 5, 2000
CadMOS Design Technology Announces ArctICtm,
An Electrical Rule Checker for SOC DesignsTool encapsulates best practice design knowledge
Los Angeles, California—Jun 5, 2000 –CadMOS Design Technology, Inc. today announced ArctICtm, an advanced electrical rule checker for system-on-chip (SOC) designers. The tool can be used to check the electrical integrity of complex digital, memory and mixed analog-digital circuits. ArctIC allows designers to easily translate their own knowledge base into a programmable set of rules, and to exhaustively check a design for rules violations. The tool enables this knowledge base to grow extensively providing the flexibility to keep up with advances in technology and changes in design practice.
"Many serious electrical problems can be avoided by exhaustively checking against a set of circuit design guidelines. This is especially true for SOC designs where a mixture of design styles (e.g. custom and cell-based digital, memory, analog) are being deployed across the chip," said Charlie Huang, CEO of CadMOS. "Using ArctIC, designers can quickly isolate hook-up problems as well as identifying anomalous circuit structures that could cause functional, timing, power or yield problems."
"ArctIC can be especially useful for SOC designs that utilize intellectual property (IP) cores," said Jim McCanny, vice-president of business development at CadMOS. "The tool can be used to ensure that all parts of your design, including blocks over which you have no control, adhere to a uniform set of design guidelines."
Static Rule Checking
Creating working SOC designs is extremely challenging. Designers must manage many complex tradeoffs between area, cost, timing, power and noise immunity while ensuring functionality. To tackle these tough demands and to enhance design productivity, design teams often adopt a set of rules to catch mistakes early in the design process. These rules help enforce a consistent design methodology so that the number of unpleasant surprises found during post-layout validation is greatly reduced along with the number of design iterations required to achieve working silicon.
ArctIC is a static rule checker that can be used to check SOC designs against electrical rules. The rules include both built-in checks and user written rules. The built-in checks include checks for issues related to circuit topology (e.g. incorrect transistor sizing), timing (e.g. latch writability) and noise immunity (e.g. charge sharing). User written rules can include design methodology checks plus additional electrical checks that are pertinent to the circuit design style being used.
Context Sensitive Rule Checking
In order to apply appropriate rules in the correct context, ArctIC uniquely classifies different circuit topologies. Each rule can then be applied with different pass/fail criteria based on these classifications. For example, ArctIC can check for different beta ratios (the ratio of effective pullup width over effective pulldown width) on static logic gates than dynamic logic gates.
Programability
ArctIC provides a very sophisticated electrical framework for advanced rule checking. Additional rules can be easily added using the extensive Tcl application program interface (API). Using this API, it is easy to create a rich customized rule set that will catch many potential errors before they are implemented in layout.
Availability, Pricing and Interfaces
ArctICtm is available now on SUN's (Nasdaq:SUNW) Solaris 2.6 and HP’s (NYSE:HWP) HPUX 10.20. Pricing starts at $17,000 U.S. list for an annual time based license including maintenance. ArctIC requires a SPICE netlist and a control file in Tcl format. ArctIC also accepts interconnect parasitics including coupling in DSPF and SPEF formats. ArctIC generates error reports in HTML format. Each failure can also be highlighted back on the schematic. Customized error reports can also be generated using ArctIC’s APIs.
For noise related problems, ArctIC has an option to check these using PacifIC. PacifIC provides a detailed simulation based noise immunity analysis that can identify true noise problems from the list of suspect nets created by ArctIC.
About CadMOS Design Technology, Inc.
CadMOS was founded in August 1997 by CAD and design experts from IBM and Synopsys/EPIC and is funded by U.S. Venture Partners, Intel Capital, Allegro Capital and private investors. The company is privately held, and is headquartered in San Jose, CA. The company provides solutions and services to reduce the "silicon reality gap"tm created by existing design flows that ignore the true UDSM electrical effects such as noise. By closing this gap, CadMOS enables their customers to "accelerate design to silicon"tm. CadMOS sells its products directly in the US and through distributors worldwide. CadMOS is located at 111 North Market, Suite 440, San Jose, CA 95113, USA. Telephone: (408) 795-1212. Fax: (408) 795-1210. Email: info@cadmos.com. Website: http://www.cadmos.com
For more information, contact:
Jim McCanny, CadMOS Design Technology, 408-535-2511 jim@cadmos.com
Pam Wasserman, Lee Public Relations, 650-363-0142 pam@leepr.com