Monday, May 22, 2000
CadMOS Design Technology Announces CeltICtm, A Full Chip Crosstalk Analyzer for ASIC and Semi-Custom ICs
Tool enables designers to mitigate effects of noise on timing and functionality
Orlando, Florida—May 22, 2000 –CadMOS Design Technology, Inc. today announced CeltICtm, a leading edge tool for combating noise in ASIC and semi-custom IC designs. CeltICtm enables ultra deep submicron [UDSM] designers to assess the impact of crosstalk on timing and functionality of their designs and to fix problems prior to tape-out.
"Many cell-based designs being manufactured at 0.18m technology or below are suffering from delayed product introductions as designers battle with crosstalk related problems such as functional failure, low yield and poor performance" said Jim McCanny, vice president of Business Development at CadMOS. "By utilizing CeltIC, cell-based designers can overcome the noise related pitfalls of designing in these technologies."
"CeltICtm was developed in response to feedback we got from COT and ASIC customers about their design challenges" said Charlie Huang, chief executive officer of CadMOS. "While it utilizes many of the breakthrough analysis capabilities that we developed for PacifICtm, it is tuned to the needs of the cell-based designer. Many of our ASIC and semi-custom customers are primarily concerned about inaccuracies in their static timing due to noise effects. When these are not considered, designers may think they are achieving timing closure; however, the silicon tells a different story. The ramification of ignoring noise effects could be lower than expected performance or yield, or worst yet, a dead chip."
Combat Delay Uncertainty
Crosstalk caused by coupling noise can wreak havoc with a design’s timing and functionality. When neighboring signals switch in opposite directions, crosstalk between them can severely increase delay, by over 100% in many cases, possibly leading to setup violations. Conversely, when neighboring signals switch in the same direction, crosstalk can decrease delay, leading to hold violations.
CeltICtm utilizes timing information from a static timer and RC extracted netlists to accurately compute crosstalk noise. It then creates an incremental SDF that can be fed back into static timing in order to refine timing computation.
"To develop CeltICtm, we extended the powerful core technology deployed in PacifICtm", said Vinod Narayanan, VP of R&D at CadMOS. "We architected CeltICtm so that it has optimal runtime and large capacity while maintaining extremely high accuracy. We are able to perform full chip analysis using our hierarchical capability."
CeltICtm supports hierarchical crosstalk analysis through the use and creation of ECHOtm noise models. For custom blocks, ECHOtm models are generated by performing analysis at the transistor level using PacifICtm or at the cell level using CeltIC. . Non-digital blocks such as analog or memory can be modeled as user defined noise models (UDNs). Through the use of these modeling schemes, CeltICtm is able to support noise analysis of multi-million transistor system-on-chip (SOC) designs.
Isolate Noise Failures
CeltICtm identifies potential noise induced functional failures using CadMOS’ advanced noise immunity check. This check, developed for PacifICtm, has been proven to reduce the number of reported false failures by at least an order of magnitude as compared with rule-based checks.
CeltICtm utilizes innovative techniques to identify which nets are most vulnerable to crosstalk noise, and then performs more detailed transistor level analysis using a built-in high-speed circuit simulation engine. By selectively using circuit simulation, CeltICtm achieves reliable accuracy while maintaining high speed and capacity for large ASIC designs.
Fix Potential Problems
To correct noise induced timing or functional problems, CeltICtm can generate design fixes that can be implemented as incremental ECOs in place and route tools. This feature facilitates more rapid design closure without overdesign.
CeltICtm can be used in conjunction with floorplanning, and place and route tools to identify and prevent noise problems throughout the design flow. It can be used to analyze crosstalk both after floorplanning with estimated coupling and later after place and route extraction.
Availability, Pricing and Interfaces
CeltICtm is available now on SUN's (Nasdaq:SUNW) Solaris 2.6 and HP’s (NYSE:HWP) HPUX 10.20. Pricing starts at $36,250 U.S. list for an annual time based license including maintenance. CeltICtm requires extracted RC parasitics in industry standard SPEF or DSPF formats, a CadMOS created noise library and a Tcl control file. CeltICtm can use signal switching windows and transitions to disallow false switching. These can be imported in the Tcl control file directly from static timing analyzers such as Synopsys’ (Nasdaq:SNPS) PrimeTimetm.
CeltICtm outputs sorted noise and "delay uncertainty" reports in HTML format for viewing with standard web browsers. Computed delta delay changes can also be exported as SDF to enable "noise aware" timing verification with static timing analyzers such as Synopsys’ PrimeTimetm.
About CadMOS Design Technology, Inc.
CadMOS was founded in August 1997 by CAD and design experts from IBM and Synopsys/EPIC and is funded by U.S. Venture Partners, Intel Capital, Allegro Capital and private investors. The company is privately held, and is headquartered in San Jose, CA. The company provides solutions and services to reduce the "silicon reality gap"tm created by existing design flows that ignore the true UDSM electrical effects such as noise. By closing this gap, CadMOS enables their customers to "accelerate design to silicon"tm. CadMOS sells its products directly in the US and through distributors worldwide. CadMOS is located at 111 North Market, Suite 440, San Jose, CA 95113, USA. Telephone: (408) 795-1212. Fax: (408) 795-1210. Email: info@cadmos.com. Website: http://www.cadmos.com
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Note to Editors:
Quote(s): Charlie Huang, Jim McCanny, Vinod Narayanan (408) 795-1212
PrimeTimetm is a registered trademark of Synopsys, Inc.
.CeltICtm, PacifICtm, ECHOtm, silicon reality gaptm and design to silicontm are registered trademarks of CadMOS Design Technology, Inc.
For more information, contact:
Jim McCanny, CadMOS Design Technology, 408-795-1212 x511 jim@cadmos.com
Pam Wasserman, Lee Public Relations, 650-363-0142 pam@leepr.com