Monday, Mar 6th, 2000
Texas Instruments Successfully Performs Noise Immunity Validation of a DSP design with CadMOS’ PacifIC
SANTA CLARA, Calif.—Mar 6th, 2000—CadMOS Design Technology, Inc. today announced that Texas Instruments (TI) has successfully used PacifIC to perform signal integrity analysis and noise immunity validation of a DSP chip. PacifIC helped in detecting two cases in the design where noise could have caused a functional failure. Based on PacifIC’s findings, TI’s designers were able to make the necessary changes prior to tape out, saving a potential silicon re-spin.
" PacifIC is a versatile tool in performing noise analysis for different logic styles." said Nagaraj N.S., Senior Member of Technical Staff at Texas Instruments, Inc., "CadMOS is very responsive to our requirements and ideas. We've successfully performed full-chip noise analysis and plan to use PacifIC on future DSP designs."
"Ensuring our high performance DSP chips are free from noise problems is essential for us to meet our market windows and quality goals." said Mike Fazeli, Worldwide EDA manager for DSP based designs at Texas Instruments Inc., "Integration of EDA point solutions into our design environment is a major requirement for ease of use. We are pleased to see CadMOS has been receptive to our suggestions for open design environment architectures and their support of standard interfaces."
"We are very pleased to see PacifIC prove it’s value on large complex production designs such as TI’s world class DSP processors," commented Charlie Huang, CEO of CadMOS. "TI was an early adopter of PacifIC and has taken proactive steps to deal with the noise epidemic that is plaguing designers using 0.18m processes or below." he added.
About PacifIC
PacifIC tm is an advanced static noise analyzer for high performance digital CMOS ICs. It exhaustively analyzes the impact of noise on digital circuits by analyzing all major sources of noise acting together in the worst allowable way. Noise sources considered include crosstalk, leakage, charge sharing and supply noise.
About CadMOS Design Technology, Inc.CadMOS was founded in August 1997 by CAD and design experts from IBM and Synopsys/EPIC. The company is privately held, and is headquartered in San Jose, CA. CadMOS provides premium solutions to the electrical problems found in leading edge IC designs. CadMOS sells its products directly in the US and through a distributor, Marubeni Solutions, in Japan.
CadMOS is located at 111 N. Market Street, Suite 440, San Jose, CA 95113-1117.
Telephone: +1-408-795-1212 Fax: +1-408-795-1210.
Email: info@cadmos.com Website http://www.cadmos.com
For more information, contact:
Jim McCanny, CadMOS Design Technology, 408-795-1212 x511 jim@cadmos.com
Pam Wasserman, Lee Public Relations, 650-363-0142 pam@leepr.com