Monday, March 29, 1999
CadMOS Design Technology Announces PacifICtm , the First Comprehensive Noise Analysis Solution for Digital ICs
Tool Identifies Functional Failures Due to Noise, Ensures Noise Immunity, Improves Yield
SAN JOSE, California—March 29, 1999 –CadMOS Design Technology, Inc today announced PacifICtm, the first commercial static noise analyzer for digital ICs. PacifICtm enables sub-0.25 micron (ultra deep submicron [UDSM]) designers developing complex digital ICs to validate the noise immunity of their design before it is manufactured.
For today's complex designs where there are millions of transistors, it is impractical to use dynamic simulation to check a design's noise immunity. PacifICtm uses static analysis combined with localized transient simulation to calculate and check the noise stability of every net in a design. It performs a complete analysis of all major noise sources acting together in the worst allowable way.
"We have been beta testing PacifIC since August," said Don Draper, circuit design manager for AMD's K6-2 microprocessor and AMD fellow, "and have used it successfully on some of our most advanced custom macro blocks. We are incorporating PacifIC into our design flow to add an extra level of robustness and reliability to our designs, by ensuring that we have caught, and corrected before tapeout, any potential noise problems. We think the tool will be increasingly useful as we migrate the K6 family to even denser processes where noise suppression is an even more dominant part of good circuit design. "
Noise in Digital Systems
In UDSM processes, geometries are so densely packed that unintended electrical interactions occur between them. These spurious electrical spikes (noise) can have significant impact on a chip's operation. In some cases performance will be degraded while in many cases the effect is more catastrophic, the chip does not function. The current trend towards "systems on chip" design using ever smaller geometries will increase the likelihood of noise failures.
Noise in digital circuits can come from many different on-chip sources. The most damaging noise sources are crosstalk between adjacent switching wires, charge redistribution in static and dynamic logic gates and power supply fluctuations. All these noise sources can interact to destabilize stored logic values and cause failures. They can cause both hard design failures where no parts will function and sporadic failures that occur only under certain process conditions. These later failures are often misdiagnosed as manufacturing yield problems when they are really due to a lack of noise immunity.
"Noise has become as important a metric as timing or power in the design of digital ICs. We are aware of many weeks of debugging on dead chips to track down elusive noise problems," said Charlie Huang, chief executive officer of CadMOS. "PacifIC can be used throughout the design process to identify design weaknesses and pinpoint noise problems. Without a way to manage the delicate trade-off between noise margin, area and performance, designers tend to over design. We believe PacifIC is the only truly comprehensive noise analysis solution available to digital IC designers."
Availability and Interfaces
PacifICtm is available now on SUN's Solaris 2.5.1, Solaris 2.6 and HP's HPUX 10.20.
PacifICtm accepts netlists in industry standard SPICE or DSPF formats and device models in BSIM 3V3 format. It outputs noise reports in HTML format for viewing with standard web browsers. The tool uses the TCL scripting language for user control. Interfaces to popular design environments from Cadence, Mentor and Synopsys are slated for release later this year.
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About CadMOS Design Technology, Inc.
CadMOS was founded in August 1997 by CAD and design experts from IBM and Synopsys/EPIC with $3M in funding from U.S. Venture Partners and private investors. The company is privately held, and is headquartered in San Jose, CA. CadMOS provides premium solutions to the electrical problems found in leading edge designs. CadMOS sells its products directly in the US and through a distributor, Marubeni Solutions, in Japan.
CadMOS is located at 111 N. Market Street, Suite 440, San Jose, CA 95113-1117.
Telephone: +1-408-795-1212 Fax: +1-408-795-1210.
Email: info@cadmos.com Website http://www.cadmos.com
Note to Editors:
Quote(s): Don Draper 408-774-7776, Charlie Huang 408-795-1212
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For more information, contact:
Jim McCanny, CadMOS Design Technology, 408-795-1212 x511 jim@cadmos.com
Pam Wasserman, Lee Public Relations, 650-363-0142 pam@leepr.com