Monday, Nov 6th, 2000
Burr-Brown Japan Purchases SeismIC, CadMOS’
Substrate Noise Analysis Tool
Burr-Brown Japan Utilizes SeismIC for Noise-free DAC Design
San Jose, CA— November 6, 2000 –CadMOS Design Technology, Inc. a leading provider of signal integrity tools, announced today that Burr-Brown Japan has purchased its SeismIC™ software. SeismIC is a substrate analysis tool that performs extraction, noise simulation and advises on techniques to minimize substrate noise. SeismIC’s extraction and simulation engines facilitate design verification, trade-off analysis and optimal noise immune designs. SeismIC will enable Burr-Brown Japan to prevent substrate noise problems and optimize noise-sensitive blocks for future mixed-signal products.
The purchase follows an extensive successful benchmark of a sigma-delta DAC converter design. Substrate noise was a key concern for this design, and the effectiveness of several isolation and power supply configurations was determined using SeismIC. "SeismIC provided valuable information regarding sources of substrate noise for our DAC converter. We are convinced that SeismIC will be a critical part of our methodology for successfully integrating analog and digital components on our chips. We were very impressed with SeismIC's features, capacity and performance" said Dr. Toshi Hamasaki, general manager of R&D at Burr-Brown Japan.
"SeismIC is highly unique because it can accurately handle substrate noise analysis at the circuit, block and full-chip levels" said Charlie Huang, CEO of CadMOS. "We are extremely pleased that SeismIC addresses issues faced by leading mixed signal design companies such as Burr-Brown Japan ."
About CadMOS Design Technology, Inc.
Founded in August 1997 by design and CAD experts from IBM and Synopsys/EPIC, CadMOS Design Technology is the leading provider of solutions and services to close the silicon reality gaptm created by design flows that ignore UDSM electrical effects. CadMOS’ founders invented static noise analysis, and these concepts have been extended to develop a powerful suite of tools, which address signal integrity issues in all design styles. Headquartered in San Jose, CA, the company maintains sales and support offices in Silicon Valley, Austin, Virginia and Japan. CadMOS customers include Texas Instruments, AMD, Lucent and National Semiconductor. CadMOS is located at 111 North Market, Suite 440, San Jose, CA 95113, USA. Telephone: (408) 795-1212. Fax: (408) 795-1210. Email: info@cadmos.com. Website: http://www.cadmos.com
About TI/Burr-Brown Japan
Texas Instruments Incorporated is a global semiconductor company and the world's leading designer and supplier of digital signal processing and analog technologies, the engines driving the digitization of electronics.
TI is a leader in the real-time technologies that help people communicate. We are moving fast to drive the Internet era forward with semiconductor solutions for large markets such as digital wireless and broadband access.
For more information, contact:
Saila Ponnapalli, CadMOS Design Technology, 408-795-1212 x529 saila@cadmos.com
Pam Wasserman, Lee Public Relations, 650-363-0142 pam@leepr.com