CADENCE EXTENDS SOC LEADERSHIP WITH ACQUISITION
OF CadMOS DESIGN TECHNOLOGY
Acquisition Adds World-Class Signal Integrity Capabilities to SP&R
and Physical Verification Design Flows
SAN JOSE, Calif. – January 4, 2001 – Cadence Design Systems, Inc. (NYSE: CDN), the world’s leading supplier of electronic design products and services, today announced that it has signed a definitive agreement to acquire CadMOS Design Technology, Inc., a privately held design tools firm headquartered in San Jose, Calif. Financial terms of the agreement were not disclosed. The acquisition is expected to be completed in the first quarter of 2001.
The CadMOS acquisition will provide CadenceÒ with world-class signal integrity analysis capability that will be incorporated into the Cadence front- and back-end SP&R design solutions, and into the AssuraÔ physical verification and extraction tool suite.
As designers migrate to ultra-deep sub-micron (UDSM) they face new challenges in order to produce high-quality, high-performance, high-yielding designs. In particular, as process technology scales and clock frequencies increase, the amount of on-chip noise increases dramatically, making signal integrity the next big problem in achieving
successful designs. "Adding CadMOS signal integrity analysis engines to established Cadence analog and digital design solutions provides us with the best correct-by-design timing and signal integrity closure capabilities in the industry," said Paul McLellan, corporate vice-president of custom integrated circuit (IC) products at Cadence. "These benefits will enable us to provide our customers with tools that substantially improve yield, performance, and predictability."
According to Charlie Huang, chairman and CEO of CadMOS, "By marrying our team and technology to Cadence -- the leading vendor in system-on-a-chip (SOC) solutions -- we can accelerate the changes in methodology and flows that are becoming necessary for designers to achieve working UDSM silicon. In fact, these products are available today and already in use at leading customers such as Lucent Technologies, Texas Instruments, Cirrus Logic, Broadcom and AMD."
About CadMOS
CadMOS was founded in 1997 to provide solutions to the noise problems experienced in UDSM processes. Its noise-analysis solutions are targeted at both digital and mixed signal designers working in microprocessors, DRAMs, mixed-signal SOC, and ASICs. CadMOS currently has 25 employees.
About Cadence
Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,200 employees and 1999 annual revenue of $1.1 billion, Cadence has sales offices, design centers, and research facilities located around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. For more information, visit http://www.cadence.com.
Except for historical information, the matters discussed in this release contain forward-looking statements based on current expectations or beliefs and are subject to factors and uncertainties that could cause actual results to differ materially from those described in the forward-looking statements. For a detailed discussion of these and other cautionary statements, please refer to Cadence’s filings with the Securities and Exchange Commission. These include the Company’s annual Report on Form 10-K for the year ended January 1, 2000 and the most recent Quarterly Report on Form 10-Q for the quarter ended September 30, 2000.
For more information, contact:
Jim McCanny, CadMOS Design Technology, 408-795-1212 x511 jim@cadmos.com
Valerie Smith, Cadence Design Systems, 408-428-5795 vsmith@cadence.com